The present invention relates, in general, to electronics and, more particularly, to packaged electronic structures and methods of forming electronic structures.
Wireless and portable handheld communication applications markets are examples of markets continuing to grow and evolve with an increased effort to integrate more electronic functionality into smaller, lighter, thinner, and lower cost solutions. One of the continuing challenges for these applications is the improvement and integration of effective antennas into the various product platforms. Several approaches have been developed and implemented in numerous form factors, but typically utilize more traditional antenna designs, such as discrete foil strips and separate retractable dipole antennas as well as combinations thereof located within or exterior to the product. Such antennas include slot antennas, inverted F antennas (“IFA”), planar inverted F antennas (“PIFA”), and various configurations of micro-strip antennas, also known as “patch” antennas.
The antennas used in wireless applications have been incorporated into product housings as separate and discrete components using materials, such as conductive strip tapes, placed into product cases using carbon based materials to form the appropriate antenna array, or included as a separate and discrete component electrically connected to the RF section of the device. Other approaches have placed the antenna as a separate component on system printed circuit boards (“PCBs”) utilizing features of the PCB and other antenna elements within the applications to complete the antenna functionality.
Each of these previous approaches adds cost to the device. Also, these previous approaches are difficult to design, consume power due to inefficient operation, add bulk to the application, and limit the absolute size and/or form factor of the application. Additionally, each solution or technique is unique to the device it is designed for, which minimizes design reuse and increases the complexity of the device design cycle, further adding to the cost and increasing the time to market for product introduction.
Another continuing challenge for electronic packaged devices is the delamination of molding compound (“EMC”) in substrate-based packaged electronic devices, such as lead frame packaged electronic devices. Delamination is often encountered during reliability stress testing and limits the use of these packaging types in certain applications and markets. Delamination beyond acceptable industry standard limits, such as those defined in JEDEC standards, is typically defined as a reliability risk and results in the device failing reliability qualification. In the past, typical corrective actions have been to change the device bill of materials and/or a redesign of the package level components such as the substrate.
The automotive industry has proposed to redefine the acceptable limits for package level delamination to be essentially zero. This desired goal is actively being pursued throughout the integrated circuit packaging and assembly industry. Current solutions being pursued and proposed have focused primarily on changes to molding compound configurations and die attach materials. Also, a significant amount of development has been applied to treatment of the substrate surfaces in the form of roughening techniques both of which can be chemically and mechanically applied. Typically in this approach, a roughening process has been applied to the surface of a substrate and has been combined with the selecting improved molding compounds and die attach materials. This approach has been shown to provide some improvement in the adhesion between the molding compound and the substrate, thereby reducing delamination. Another approach has been to include protrusions or half-etched portions within the substrate and/or leads, which acts to increase the surface area for adhering to the molding compound. These features also have been used to provide lead stabilization.
However, for larger body devices, (e.g., devices with large die pads greater than 4 millimeters (mm) by 4 mm), devices with long tie bar configurations (e.g., tie bar having lengths greater than about 3 mm), or devices with a high usage of die-to-die attach pad wire bonds, commonly known as down bonds, and combinations thereof, the present solutions have not provided satisfactory results.
Accordingly, structures and methods are needed that provide improved antenna designs to support, among other things, the industry demands for increased electronic functionality within smaller, lighter, thinner, and lower cost solutions. Also it would be beneficial for such structures and methods to be cost effective by using, for example, existing assembly processes and techniques. Additionally, structures and methods are needed for reducing delamination in electronic packages including, for example, the package structures disclosed hereinafter. Further, it would be beneficial for such structures and methods to reduce stresses within the package structures to further improve reliability.
For simplicity and clarity of the illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. It will be appreciated by those skilled in the art that the words during, while, and when as used herein relating to circuit operation are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay(s), such as various propagation delays, between the reaction that is initiated by the initial action. Additionally, the term while means that a certain action occurs at least within some portion of a duration of the initiating action. The use of the words about, approximately or substantially means that a value of an element has a parameter that is expected to be close to a stated value or position. However, as is well known in the art there are always minor variances that prevent the values or positions from being exactly as stated. It The terms first, second, third and the like in the claims or/and in the Detailed Description of the Drawings, as used in a portion of a name of an element are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments described herein are capable of operation in other sequences than described or illustrated herein. Additionally, it is to be understood that where it is stated herein that one layer or region is formed on or disposed on a second layer or another region, the first layer may be formed or disposed directly on the second layer or there may be intervening layers between the first layer and the second layer. Further, as used herein, the term formed on is used with the same meaning as located on or disposed on and is not meant to be limiting regarding any particular fabrication process. Moreover, the term “major surface” when used in conjunction with a semiconductor region, wafer, or substrate means the surface of the semiconductor region, wafer, or substrate that forms an interface with another material, such as a dielectric, an insulator, a conductor, or a polycrystalline semiconductor. The major surface can have a topography that changes in the x, y and z directions.